[PDF][PDF] Bringing the high end to the low end: high performance device drivers of the Linux PC
R Geist, J Westall?- Proceedings of the 36th annual ACM Southeast?…, 1998 - dl.acm.org
Specialized, high-performance computing devices for tasks such as graphics, communi~
tions, and storage, once available only on high-end systems, are now available as add-ens for …
tions, and storage, once available only on high-end systems, are now available as add-ens for …
[PDF][PDF] CAMPORT-an intelligent interface between CAMAC and a microcomputer bus
MR Meyer, P Schmid, S Carius - 1983 - cds.cern.ch
… This allows DMA and interrupt handling for the microcomputer, whilst being completely
CAMAC compatible. …
CAMAC compatible. …
[PDF][PDF] User–mode device driver development
A Gutheil, B Weisser?- Advanced Microkernel Operating Systems, 2015 - cs.hs-rm.de
… The kernel adapter is responsible for memory allocation via DMA and interrupt handling,
which is partially based on the already introduced UIO approach. Like U2MDF, PDA realizes a …
which is partially based on the already introduced UIO approach. Like U2MDF, PDA realizes a …
High-visibility debug-by-design for FPGA platforms
P Bellows?- The Journal of Supercomputing, 2005 - Springer
… The only driver operations implemented in the kernel are raw DMA and interrupt handling,
which require privileged and/or atomic execution. This two-layer approach greatly simplifies …
which require privileged and/or atomic execution. This two-layer approach greatly simplifies …
Virtualizing high-performance graphics cards for driver design and development
Operating system virtualization tools such as VMWare, XEN, and Linux KVM export only
minimally capable SVGA graphics adapters. This paper describes the design and …
minimally capable SVGA graphics adapters. This paper describes the design and …
An eye on design: Effective embedded system software
SP Kamat?- IEEE Potentials, 2010 - ieeexplore.ieee.org
Good software design is as important in the development of a product as a strong foundation
in the construction of an edifice. This is particularly important in the development of an …
in the construction of an edifice. This is particularly important in the development of an …
SpliceNP: a TCP splicer using a network processor
… We can see from the figure that the DMA and interrupt handling (t0-t3) totally take about 11.7
us, whereas this part is almost negligible in the NP implementation when Figure 4(b) or (c) …
us, whereas this part is almost negligible in the NP implementation when Figure 4(b) or (c) …
A peripheral-oriented microcomputer system
JE Bass?- Proceedings of the IEEE, 2005 - ieeexplore.ieee.org
… Each controller contains command decode logic, status registers, data registers, address
decode logic, and DMA and interrupt handling logic as well as interface control logic which …
decode logic, and DMA and interrupt handling logic as well as interface control logic which …
Function-microcomputers for computer graphics
G Szanto, J van den Bos?- Euromicro Newsletter, 1980 - Elsevier
… These components include memory chips (ROM, PROM, EPROM, RAM), function circuits
for communication, peripheral I/0, DMA and interrupt handling, complete arithmetic circuits for …
for communication, peripheral I/0, DMA and interrupt handling, complete arithmetic circuits for …
FPGA bootstrapping on PCIe using partial reconfiguration
PS Ostler, MJ Wirthlin, JE Jensen?- …?International Conference on?…, 2011 - ieeexplore.ieee.org
For many FPGA-based computing systems, a dedicated FPGA or interface chip is included
to provide I/O functionality. As commercial FPGA sincrease in size, they are becoming large …
to provide I/O functionality. As commercial FPGA sincrease in size, they are becoming large …